1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to the configuration of data writing/reading circuitry in a semiconductor memory device having a plurality of data input/output nodes (I/O terminals). More particularly, the present invention relates to a configuration for efficiently testing a semiconductor memory device having a plurality of data input/output terminals.
2. Description of the Background Art
In semiconductor memory devices, various tests are performed in order to insure the reliability of products. One such test includes a fault detection test to detect whether or not data is accurately written/read out. In such a test, a single testing apparatus is used to simultaneously observe a plurality of semiconductor memory devices. In such a case, the number of semiconductor memory devices which can be observed at a time depends on the number of data input/output terminals of each semiconductor memory device. During writing/reading test data using all the 16 data input/output terminals of a 16-I/O-semiconductor memory device, the number of devices can be observed at a time is 1/2 that of an 8-I/O-semiconductor memory device having 8 data input/output terminals. Therefore, if a multi-I/O-semiconductor memory device having a plurality of data input/output terminals can be tested using a reduced number of data input/output terminals (I/O) (I/O compression), the number of semiconductor memory devices which can be measured at a time can be increased, thereby allowing efficient testing of the devices.
FIG. 24 is a diagram schematically showing an overall configuration of a semiconductor memory device having a conventional I/O compression circuit. In FIG. 24, semiconductor memory device 500 includes memory arrays 502a, 502b, 502c and 502d each having a plurality of memory cells, X decoders 504a, 504b, 504c and 504d provided respectively to memory arrays 502a to 502d for decoding an applied X address signal and driving an addressed row in a corresponding memory array into a selected state, and Y decoders 506a to 506d provided respectively to memory arrays 502a to 502d for decoding an applied Y address signal and simultaneously selecting memory cells of 4 bits in a corresponding memory array.
Semiconductor memory device 500 has 16 bit--data input/output terminals labeled terminal I/O&lt;0-15&gt;, and memory cells of 4 bits are selected at a time in each of memory arrays 502a to 502d. The memory cells of 4 bits selected at a time in each of memory arrays 502a to 502d are coupled to internal data buses 508a, 508b, 508c and 508d provided respectively to memory arrays 502a to 502d.
Semiconductor memory device 500 further includes an input/output circuit 510 for receiving externally applied data input and externally outputting data through data input/output terminal I/O&lt;0-15&gt;, a test mode detection circuit 512 for detecting a test mode being specified based on the states of externally applied control signals, in other words a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE, a compression circuit 514 for compressing 16-bit memory cell data read out on internal data buses 508a to 508d into 1-bit data, and a selector circuit 516 for selecting a data transfer path between input/output circuit 510 and internal data buses 508a to 508d in response to a test mode activation signal .phi.TM from test mode detection circuit 512.
Input/output circuit 510 transfers data DI&lt;0&gt; among writing data DI&lt;0-15&gt; applied to data input/output terminal I/O&lt;0-15&gt; to an internal writing data bus 515a, and the remaining 15 bit writing data DI&lt;1-15&gt; to a writing data bus 515b, and outputs in parallel 16-bit data DO&lt;0-15&gt; provided from selector circuit 516 on an internal reading data bus 515c to data input/output terminal I/O&lt;0-15&gt;.
Selector circuit 516 has an input node TMI coupled to internal writing data bus 515a, an input node NMI coupled to internal writing data bus 515b, a data output node DO&lt;0-15&gt; coupled to internal reading data bus 515c, a node TMO receiving the output signal of compression circuit 514, data input/output nodes IO&lt;0-3&gt;, IO&lt;4-7&gt;, IO&lt;8-11&gt;, and IO&lt;12-15&gt; coupled to internal data buses 508a to 508d, respectively, and a test mode signal input node TM receiving test mode activation signal .phi.TM. Now, the operation will be briefly described.
In memory arrays 502a to 502d, memory cells of four bits are simultaneously selected by X decoders 504a to 504d and Y decoders 506a to 506d, and these selected memory cells are coupled to corresponding internal data buses 508a to 508d.
During data writing in a normal operation mode, test mode activation signal .phi.TM is in an inactive state. In this state, selector circuit 516 transfers data DI&lt;0&gt; and DI&lt;1-15&gt; provided onto internal writing data buses 515a and 515b from input/output circuit 510 to internal data buses 508a to 508d, respectively. As shown in FIG. 24, memory arrays 502a to 502d correspond to I/O&lt;0-3&gt;, I/O&lt;4-7&gt;, IO&lt;8-11&gt; and IO&lt;12-15&gt;, respectively. Thus, 16 bits of data are simultaneously written.
During reading data in a normal mode of operation, selector circuit 516 transfers data read out on internal data buses 508a to 508d onto internal reading bus 515c, because test mode activation signal .phi.TM is in an inactive state. Input/output circuit 510 has its output circuit portion activated, and outputs in parallel data DO&lt;0-15&gt; on internal reading bus 515c to data input/output terminal I/O&lt;0-15&gt;.
When test mode activation signal .phi.TM is in an active state, during writing data, selector circuit 516 selects data DI&lt;0&gt; (TMI) provided onto internal writing bus 515a from input/output circuit 510 to internal data buses 508a to 508d. Thus, the same data is simultaneously written to memory cells of 16 bits. During reading out data, compression circuit 514 compresses the 16 bit-data read out on internal data buses 508a to 508d through a prescribed logic processing, into 1-bit data for application to the node TMO of selector circuit 516. When test mode activation signal .phi.TM is activated, selector circuit 516 selects the compressed data applied to node TMO and applies the selected data to input/output circuit 510 as DO&lt;0&gt; for output to data input/output terminal I/O&lt;0&gt;.
Therefore in the semiconductor memory device as shown in FIG. 24, in the test mode, test data can be written and test result data can be read out using a single data input/output terminal I/O&lt;0&gt;, and the number of data input/output terminals used for testing can be reduced.
FIG. 25 is a diagram showing an example of the configuration of compression circuit 514 shown in FIG. 24. In FIG. 25, compression circuit 514 includes 8 coincidence detection circuits (EXOR circuits) 510a, 514b . . . 514h each receiving 2-bit data of a prescribed combination among 16 bit-data D0 to D15 read out onto internal data buses 508a to 508d (see FIG. 24), an NOR circuit 514i receiving the output signals of these coincidence detection circuits 514a to 514h, and an inverter circuit 514j receiving the output signal of NOR 514i. Compression test result data TMO is output from NOR circuit 514i, and inverted compression test result data ITMO (a node and a signal on the node are denoted by the same reference character) is output from inverter circuit 514a.
In the configuration of compression circuit 514 shown in FIG. 25, if the logic levels of reading data D0 to D15 are all in coincidence, the output signal TMO of NOR circuit 514i attains an H level ("1"). If data D0 to D15 includes "0" (L level) data and "1" (H level) data, the output signal of at least one of coincidence detection circuits 514a to 514h attains an H level, and the output signal TMO of NOR circuit 514i attains an L level ("0") accordingly. If, therefore, it is externally determined whether test result signal TMO is at an H level or an L level, it can be determined whether all the logic levels of data D0 to D15 are in coincidence, or different logic data are mixedly present, and the presence/absence of a fault in the memory cells of 16 bits selected at a time can be identified.
In the configuration of compression circuit 514 shown in FIG. 25, however, if a pair of data both have a logic level inverted from that of writing data, the output signal of the coincidence detection circuit is a signal representing a normal state (L level). If, therefore, an address storing "FFFF (HEX)" is erroneously accessed while an address storing "0000 (HEX)" should be accessed, for example, the fault cannot be detected. Therefore in the compression circuit as shown in FIG. 25, the fault/non-fault of a memory cell cannot be accurately determined.
FIG. 26 is a diagram showing another configuration of the compression circuit shown in FIG. 24. In FIG. 26, an output circuit 510a to output compression test result data is also shown.
In FIG. 26, compression circuit 514 includes an NAND circuit 514k receiving internal reading data D0 to D15, an NOR circuit 514l receiving internal reading data D0 to D15, an NOR circuit 514m receiving the output signal of NAND circuit 514k and the output signal of NOR circuit 514l, an EXOR circuit 514n receiving the output signal of NAND circuit 514k and the output signal of NOR circuit 514l, an inverter circuit 514o receiving the output signal of NOR circuit 514m, an NOR circuit 514p receiving the output signal of inverter circuit 514o and the output signal of EXOR circuit 514n, and an NOR circuit 514q receiving the output signal of NOR circuit 514m and the output signal of EXOR circuit 514n. Compression test result data is output through node TMO from NOR circuit 514p, and inverted compression test result data is output through node ITMO from NOR circuit 514q.
Output circuit 510a is included in input/output circuit 510 shown in FIG. 24, and outputs the compression test result data to data input/output terminal I/O&lt;0&gt;. Output circuit 510a includes an n channel MOS transistor 510aa connected between the power supply node and the output node and having a gate receiving the output signal of NOR circuit 514p in compression circuit 514, and an n channel MOS transistor 510ab connected between the output node and the ground node and having a gate receiving the output signal of NOR circuit 514q. Now, the operation of the compression circuit as shown in FIG. 26 will be described.
When the logics of internal reading data D0 to D15 are all "1" (at H level), the output signal of NAND circuit 514k is at an L level, and the output signal of NOR circuit 514l is at an L level. The output signal of NOR circuit 514m attains an H level as a result, and the output signal of inverter circuit 514o attains an L level accordingly. Since EXOR circuit 514n receives L level signals at both inputs, the output signal of the circuit attains an L level. Therefore, the output signal of NOR circuit 514p attains an H level, and the output signal of NOR circuit 514q attains an L level. In output circuit 510a, MOS transistor 510aa is turned on, while MOS transistor 510ab is turned off, and output signal OUT attains an H level. More specifically, if internal reading data D0 to D15 are all at an H level, an H level signal is externally output.
If internal reading data D0 to D15 are all at an L level ("0"), the output signal of NAND circuit 514k attains an H level, and the output signal of NOR circuit 514l attains an H level. In this state, the output signal of NOR circuit 514m attains an L level, and the output signal of inverter circuit 514o attains an H level. EXOR circuit 514n receives H level signals at its both inputs, and therefore the output signal from the circuit 514n attains an L level accordingly. Therefore, an L level signal is output from NOR circuit 514p, and an H level signal is output from NOR circuit 514q. Therefore, in output circuit 510a, MOS transistor 510aa is turned off, and MOS transistor 510ab is turned on, and output signal OUT attains an L level. More specifically, if internal reading data D0 to D15 are all at an L level, output signal OUT also attains an L level.
If internal reading data D0 to D15 include both H level data and L level data, the output signal of NAND circuit 514k attains an H level, and the output signal of NOR circuit 514l attains an L level. The output signal of NOR circuit 514m attains an L level accordingly, and the output signal of inverter circuit 514o attains an H level. EXOR circuit 514n receives an H level signal and an L level signal, and therefore the output signal of the circuit 514n attains an H level. The output signals of NOR circuits 514p and 514q both attain an L level, MOS transistors 510aa and 510ab are both turned off accordingly, and output circuit 510a attains an output high impedance state. More specifically, if a fault is present in a memory cell, and H level data and L level data are mixedly present, output circuit 510a attains an output high impedance state.
Therefore, in the configuration shown in FIG. 26, the presence/absence of a fault in simultaneously selected memory cell data can be determined, and the presence/absence of all bit inversion can be identified by comparing the logic levels of the read out data and written data.
However, if an output high impedance state is attained in the presence of a fault cell, using the compression circuit as shown in FIG. 26, it is difficult to determine if the output is in a high impedance state in a short test data reading cycle as will be described.
FIG. 27 is a diagram showing a configuration for identifying an output high impedance state. In FIG. 27, the output node of output circuit 510a is connected to a signal line 515. Signal line 515 is connected to a resistor R receiving intermediate voltage VT at its one end. Signal line 515 has parasitic capacitance C. By identifying the voltage level on signal line 515 using a testing apparatus, the logic of compression test result data is determined. Intermediate voltage VT is at the voltage level intermediate between power supply voltage Vdd and ground voltage Vss.
Signal line 515 is driven to the power supply voltage Vdd level by MOS transistor 510aa or discharged to the ground voltage level through MOS transistor 510ab when a selected memory cell is normal. When output circuit 510a attains an output high impedance state, signal line 515 has its voltage level changed from the H level voltage or L level voltage to the intermediate voltage VT level. The voltage changing rate of signal line 515 depends on its time constant determined by resistor element R and parasitic capacitance C.
Therefore, as shown in FIG. 28, if the voltage level is changed from H level voltage VOH or L level voltage VOL to intermediate voltage VT, the voltage change of signal line 515 becomes gentle due to the time constant of resistor element R and parasitic capacitance C. More specifically, the time T2 until a high impedance state is determined (the time required for the voltage level to change from H level voltage VH or L level voltage VOL to intermediate voltage VT)increases.
In order to determine the output high impedance state of output circuit 510a in a shorter time period, the resistance value of resistor element R should be reduced and the time constant by resistor element R and parasitic capacitance C should be reduced. However, if the resistance value of resistor element R is reduced, signal line 515 is connected to the node supplying intermediate voltage VT through reduced resistance, in which case signal line 515 cannot be driven to power supply voltage Vdd level, or to the ground voltage level (the voltage level is determined based on the ratio of the resistance value of resistor element R and the on resistance of MOS transistor 510aa or 510ab), and the amplitude of signal line 515 is reduced, which makes it difficult to accurately determine the H level and L level.
If the voltage of signal line 515 fully swings, the time required for charging to the power supply voltage Vdd level through MOS transistor 510aa or time T1 until signal line 515 is discharged to the ground voltage level through MOS transistor 510ab is increased, and time required for determining the H level and L level of the output of output circuit 510a is increased, in other words the testing cycle time cannot be reduced. As a result, the resistance value of resistor element R cannot be reduced, and the high impedance state cannot be determined in a short time period, which makes it difficult to reduce the testing cycle time.
Furthermore, in the compression circuit as shown in FIGS. 25 and 26, data of the same logic is written as data D0 to D15. Therefore, a test requiring data to be changed for each data input/output terminal in order to detect a fault due to cross talk of internal data bus or the like cannot be conducted.